Introduction of RgGen

Transcript

1. Introduction of RgGen Taichi Ishitani
2. Agenda 1. About Me 2. What is CSR? 3. Why need CSR generation? 4. What is RgGen? 5. Using RgGen 6. Usecase at PEZY
3. About Me • Taichi Ishitani ◦ GitHub (https://github.com/taichi-ishitani) ◦ Linkedin (https://www.linkedin.com/in/taichi-ishitani-28237370/) • Work for ◦ PEZY Computing K.K. (https://www.pezy.co.jp) ◦ Integrating PCIe IP ◦ Maintain common RTL modules/UVM components ▪ PZBCM (https://github.com/pezy-computing/pzbcm) ▪ PZTB (https://github.com/pezy-computing/pztb-core) ◦ Develop utility tools ▪ FLGen (https://github.com/pezy-computing/flgen)
4. • Acronym of Configuration and Status Register • A Functional block has one or more CSR blocks • Used for communication between host processor and functional blocks ◦ Each CSRs has own address ▪ Host processor can specify a CSR ◦ Write data to a CSR ▪ Updating a setting of a functional block ◦ Read data from a CSR ▪ Getting a status of a functional block • Register map ◦ List of CSRs/Specification of a CSR block ◦ You need to implement a CSR block that matches the register map What is CSR?
5. Why need CSR generation? • Manual CSR coding probems ◦ Not difficult but easy to make mistakes ▪ A lot of similar but little different code blocks • offset address, bit position, read/write action, etc. ◦ Need to write various kinds of file ▪ RTL, UVM RAL, C header, documemts ◦ Mismatch between specifications and implementations • How to resolve? ◦ Generate CSR files from register map specifications
6. What is RgGen? • Open source CSR generation tool ◦ https://github.com/rggen/rggen ◦ Written in Ruby • Readable register map format ◦ Ruby with description APIs ◦ YAML/JSON/TOML ◦ Spreadsheet • Various outputs ◦ RTL (SystemVerilog/Verilog/VHDL) ◦ UVM RAL ◦ C header ◦ Markdown
7. What is RgGen? • Support various types of registers and bit fields ◦ array register, external register, indirect register ◦ 42 types of bit fields ◦ You can generate complex registers • Support standard bus protocols ◦ APB, AXI4 Lite, Wishbone • Plugin feature ◦ You can customize RgGen by creating your own plugin ▪ Add special bit field type support ▪ Add your own bus protocol support
8. Using RgGen • You can get detail information from the project Wiki ◦ https://github.com/rggen/rggen/wiki • You can get sample files from the repository below ◦ https://github.com/rggen/rggen-sample • You can also get sample TBs as integration samples ◦ https://github.com/rggen/rggen-sample-testbench
9. Using RgGen - Installation • Install RgGen directly ◦ $ gem install rggen rggen-verilog rggen-vhdl $ rggen -v • Using Docker ◦ $ wget https://raw.githubusercontent.com/rggen/rggen-docker/master/exe/rggen-docker $ chmod +x rggen-docker $ ./rggen-dokcer -v
10. Using RgGen - Creating input files • Configuration file ◦ Specify address width, data width and host bus protocol ◦ Written in YAML, JSON or TOML ◦ https://github.com/rggen/rggen-sample/blob/master/config.yml • Register map specifications ◦ Describe CSR design information ▪ register • name, offset address, type, etc. ▪ bit field • name, bit assignment, type, initial value, etc. ◦ https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml
11. Using RgGen - Generating CSRs • Give input files to the rggen command ◦ $ rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl -o out uart_csr.yml ◦ $ rggen-docker -c config.yml -o out uarg_csr.yml ▪ -c config.yml • Specify your configuration file ▪ --plugin rggen-verilog/--plugin rggen-vhdl • Enable Verilog and VHDL plugins ▪ -o out • Specify the output directory ◦ RgGen will output generated files to the out directory
12. Usecase at PEZY • We already have integrated RgGen with our development flow • Before integration ◦ Each module designer implements CSR modules by their style ▪ Need to look into RTL code to check behavior of a CSR ◦ Mismatch between documentations and implementations • After integration ◦ Generate all CSR modules by RgGen ▪ Use YAML format for register map specifications • YAML format is good for readability and version managiment ◦ Generate Markdown documents every updating a project repository ▪ Avoid mismatch between specification, implementation and documentation