Now Anyone Can Be A Chip Designer - Open Source Tools for the Next Generation of Chip Makers

It has been evident that there is a skills gap in semiconductor design, with chip design locked behind proprietary tools. This talk will touch on an open source blueprint to address this gap with hands-on education. It will cover the RISC-V ISA, open source EDA tools (like OpenLane), and accessible fabrication via Multi-Project Wafer services dismantle these barriers. It will touch on a framework for guiding students from digital logic concepts to submitting their own designs for fabrication thereby transforming them from passive users into active creators of silicon products. This practical pathway leans on the global open source hardware community to build vital skills and inspire the next generation of innovators.

https://eventyay.com/e/88882f3e/session/10425

Transcript

1. Now Anyone Can Be A Chip Designer Open Source Tools for the Next Generation of Chip Makers Harish Pillay h.pillay@ieee.org Fellow IES, Fellow SCS, Life Member IEEE, AIGP, RHCE, MSEE, 9V1HP This deck was created using claude.ai from my speaker notes and topics provided to it in a markdown file
2. Who Am I? Harish Pillay • Grad school EE late 1980s • Designed & fabricated my first chip in 1989 - a 2×2 multiplier (via EE 518, Winter ‘90) • Tektronics, HPUX, SPICE etc • Sent using FTP over ARPAnet to MOSIS for fabrication • Die returned, tested … and eventually misplaced 😄 • It was an ah-ha moment for me • But constraint for individuals meant alternative paths need to be taken The chip I designed in 1989 started this whole journey - sort of ftp via ARPAnet → MOSIS → (postal mail) Die
3. Circuit layout of a 2x2 multiplier
4. The Problem Chip design has always been locked behind walls and big bucks 💰 Expensive Tools Proprietary EDA software can cost hundreds of thousands of dollars per seat per year 🔒 NDAs Everywhere Even accessing a foundry's design rules (Process Design Kit - PDK) required signing non-disclosure agreements ⏳ Long Timelines From concept to fabricated chip: years of work, millions in investment And the open source revolution changed everything …
5. How a Chip Gets Made - a 101 1 📋 Spec Customer requirements & product vision 2 ⚙ Logic Design Gates, memory, and netlists in HDL 3 🔲 Physical Layout Place & route on actual silicon area 4 ✅ Sign-Off Testing, verification & DRC checks 5 🏭 Foundry TSMC, Samsung, GlobalFoundries … Every stage used to require expensive proprietary software - not anymore.
6. Hardware Description Language Think of HDL as the source code for hardware. • Describe what you need (e.g. a NAND gate) • Describe how components wire together • Tools translate this into actual transistor layouts • Popular flavours: Verilog, SystemVerilog, TL-Verilog, VHDL Just like learning Python opens doors to software, learning HDL opens doors to hardware. SystemVerilog example: module toplevel(clock, reset); input clock; input reset; reg flop1, flop2; always @ (posedge reset or posedge clock) if (reset) begin flop1 <= 0; flop2 <= 1; end else begin flop1 <= flop2; flop2 <= flop1; end endmodule HDL designs are temporal and timing is not something regular programming languages handle
7. The Open Source Chip Stack Every stage now has a free, open tool — just like software development TOOL DOES WHAT SOFTWARE ANALOGY ✍ TL-Verilog / SystemVerilog Writing your design Source code (.py, .js) ⚙ Yosys Synthesis Compiler 🔗 OpenROAD / OpenLane Place & Route Linker / build system 🔍 Magic / KLayout Physical verification Debugger / linter 📦 GDS (output file) Final layout file Executable / binary
8. The Game Changer: Open Process Design Kits BEFORE • PDKs requires Non Disclosure Agreements • Locked behind corporate relationships • No signed NDA == No access to design rules • Only companies/universities could fab chips • Individuals locked out entirely AFTER (2020s) • Google encouraged Skywater to open-source their SKY130nm PDK • No NDA required => just use it! • SkyWater, GF180, IHP130 all open now • Anyone can submit a chip design (that complies to the PDK) • Many more foundries are making PDKs available • Check https://wafer.space • Growing community of global tinkerers
9. Multi-Project Wafer (MPW) Share the wafer, share the cost — democratise fabrication One Wafer Many Designers • A single silicon wafer is shared by many independent designers • Each coloured tile => a different design • Cost is split across all participants • Google's Open MPW program: free shuttles for open source designs • Tiny Tapeout: sub-$500 to get your design fabricated
10. RISC-V: Build Your Own CPU 🔓 Open ISA No royalties. No licensing fees. RISC-V is an open Instruction Set Architecture (ISA) • Unlike ARM or x86, RISC-V is free to implement for anyone • RISC-V Instruction Set Architecture is on a Creative Commons license • Massive momentum: used in smartphones, embedded systems, HPC • You can design your own RISC-V CPU with open tools today! • Some background about this at talk I gave at FOSSAsia 2023 - link in resources You can build RISC-V ISA using entirely open source tools, today. If you feel that you missed out the HTML/Web revolution of the mid-1990s, don’t miss this democratised chip design revolution.
11. Tiny Tapeout The easiest on-ramp to getting your design fabricated usually less than $500 1⃣ Design your circuit Use Wokwi (browser-based) or write HDL code. No special software needed to start. 2⃣ Submit to Tiny Tapeout The platform runs OpenLane automatically and checks your design fits the tile. 3⃣ Wait for fabrication Your design goes on a shared MPW wafer with hundreds of others. 4⃣ Get your chip! Real silicon returned to you. Test it on a provided carrier PCB. tinytapeout.com
12. Your Toolkit: Start Today - just a sampling Wokwi wokwi.com Browser-based digital logic simulator -> no install needed. Start here! Tiny Tapeout tinytapeout.com Submit your design for real fabrication. Step-by-step guides included. RedwoodEDA redwoodeda.com Learn TL-Verilog and modern hardware design with great tutorials using makerchip. VLSI System Design vlsisystemdesign.com Complete course: digital logic all the way to chip layout. AI in Chip Design ACM Sigarch 2024 article Curious about LLMs designing circuits? This ACM article covers the state of the art. Wafer.Space Singapore-based budget silicon manufacturing using Global Foundries Wafer.Space
13. LibrePDK - https://libresilicon.com/ • Generic schematic/netlist editor • Automatically generates geometries for a target node based on target parameters • Outputs Magic VLSI files which can be easily edited • Further analog property optimization using OpenEvolve in a last stage • Check out the LibreSilicon talks at the upcoming FSic2026 from July 6 to 8 2026 (https://wiki.f-si.org/index.php?title=FSiC2026)
14. LibrePDK schematics: generic schematic with target parameters LibrePDK - https://libresilicon.com/
15. ngspice simulation LibrePDK - https://libresilicon.com/
16. Autogenerated layout LibrePDK - https://libresilicon.com/
17. And one more thing … and I am pleased to have contributed to …
18. ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS)
19. ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS) The ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS) is ASEAN’s flagship strategy for becoming the centre for global semiconductor value chain given all the global dynamics. The official report will be published in April/May 2026 and here’s an early preview of the part that discusses open source tooling. Under Strategic Thrust 2: Technology Innovation, Transfer and Sharing: “c. Advance open source and collaborative innovation in semiconductor design Open source tools, technologies, and collaborative models have become integral across various industries. The United Nations Open Source Principles, adopted in February 2025, provide a comprehensive framework to foster open source development, particularly in semiconductor design and capacity building. This initiative rests upon the following activities:
20. ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS) - Adoption of RISC-V instruction set architecture To further enhance and cultivate a chip design ecosystem, ASEAN should consider adopting the RISC-V Instruction Set Architecture. This architecture offers a cost- effective solution for design systems, making it an ideal foundation for regional innovation and growth in semiconductor technology. - Promoting patent sharing and rapid innovation In addition to leveraging open source principles, establishing a patent commons for active patent sharing will accelerate innovation. This collaborative approach will enable rapid advancements in technology and strengthen the semiconductor industry within ASEAN. By integrating these strategies, ASEAN can position itself at the forefront of semiconductor design and development, driving economic growth and technological leadership.
21. ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS) - Establishing a Regional Task Force on Open Source Technology and Intellectual Property (IP) To operationalise these strategies, ASEAN should establish a Regional Task Force dedicated to open source technology - with emphasis on RISC-V -and IP. The Task Force will build a shared IP library and common design tools based on RISC-V, enabling small and medium enterprises (SMEs) to lower entry costs and overcome technical barriers. It will also develop mechanisms for IP sharing and protection, deliver training and workshops, and connect ASEAN stakeholders with global RISC-V initiatives. This initiative will enhance technological self-reliance, promote innovation, and strengthen ASEAN’s integration into global semiconductor supply chains.
22. Resources 🌐 https://www.youtube.com/watch?v=RtDalxij5WM Harish’s FOSSAsia 2023 Talk on RISC-V Thank you · Let’s talk · Harish Pillay h.pillay@ieee.org 🌐 https://www.youtube.com/watch?v=ihz2WY-E2C8 Asianometry: Designing Billions of Circuits with Code 🌐 https://tinyurl.com/libresilicon Libresilicon Signal group on Free and Open Source Semiconductors 🌐 https://libresilicon.com Libresilicon - Semiconductor Freedom For Everyone