Antoni Gelonch - Software Radio

Transcript

1. Software Radio Antoni Gelonch Mobile Communications Research Group (GRCM) Signal Theory and Communications Dept. Universitat Politècnica de Catalunya Supelec, 19 April 2007
2. Software Defined Radio (SDR) SDR is a set of HW/SW technologies that should facilitate the use of system with reconfigurable architectures in the wireless networks. Interest? SDR is an efficient way and a cheap solution to solve the problem to develop multimode, multiband and multifunction devices that can be adapted, updated and improved through software updates. Software Radio – Functional Vision
3. Militar Escenario
4. Civil Escenario New Technologies for Radio Systems: Multiservice, multi-estandard, multi-band: reconfigurables? User Needs •Multiples Locations •Multiples Environments •Multiples Radio Interfaces •InterNetworks Connectivity
5. Software Radio: is defined as a radio system where digitalization is made in the antenna and all the signal processing is done by means of software using reconfigurable high speed processors. Different systems with performances defined by Software Software Instalation and Update: • in manufacture • by memory modules • via downstreaming Software Radio – Concept Antenna Beam forming, Interference reduction, SDMA (Space Division Multiple Access), Diversity Inteligent Antennas, Arrays RF Conversion FI Processing Base Band Bits Flow Source RF/FI Filtering Power Amplifier RF to FI Conversion Sampling. AD & DA Digital Channel Filtering Base Band Conversion Frequency Synthesis Carrier Recovery Modulation/Demodulation Pre-distortion Channel Estimation Equalisation Decodification Synchronization Users Multiplexing Estimation and Quality Control Frame alignment Encryption Signalling, Control, Management and Maintenance Voice and Video Codecs, etc Generic Transmitter/Receiver SOFTWARE
6. Software Radio: is defined as a radio system where digitalization is made in the antenna and all the signal processing is done by means of software using reconfigurable high speed processors. Software Radio – Concept Antenna Beam forming, Interference reduction, SDMA (Space Division Multiple Access), Diversity Inteligent Antennas, Arrays RF Conversion FI Processing Base Band Bits Flow Source RF/FI Filtering Power Amplifier RF to FI Conversion Sampling. AD & DA Digital Channel Filtering Base Band Conversion Frequency Synthesis Carrier Recovery Modulation/Demodulation Pre-distortion Channel Estimation Equalisation Decodification Synchronization Users Multiplexing Estimation and Quality Control Frame alignment Encryption Signalling, Control, Management and Maintenance Voice and Video Codecs, etc Generic Transmitter/Receiver Technology Status Conversion Digital to Analog point Analogic Digital 01001100110…
7. Computing Demand Depends on the signal bandwidth (information size) and the complexity of the operation performed inside each one of the processing segments: FI, base-band, data flow control and data source. D=D FI +N*(D bb +D bs +D s )+D o D FI: FI demand, D bb: Base band demand, D bs: Data Flow control demand, D s: Source demand, D o: Additional demand for signalling to access to the radio network N: number of simultaneous users Segment Parameter Illustrative values Computing Demand Wa 10 MHz (oversamplig 2.5) FI FI Filter 100 Ops/Hz DFI=2500 MIPS* Users N 30/cell Wc 30 kHz Base Band Demodulator 50 Ops/Hz Dbb=1.5 MIPS Rb 32 kb/s Bits Flow FEC, signalling 100 Ops/b/s Dbs=3.2 MIPS Source Codec CELP 1.6 MIPS/user Ds=1.6 MIPS/user Signalling SS7 2 MIPS/Base Station Do=2 MIPS Addition MIPS DSP D=142.6 MIPS * DFI not incluyed in D Software Radio – Concept
8. •Digital to Analog Conversion •Computing Management SDR: Main Hardware Implications
9. SDR Platforms: Heterogeneous Distributed Computing Hardware Platform Composed of multiple processors (different) that provides the computational and communication requirements demanded by and SDR application • Layered System • Multithread Processing (Parallelism) • Modularity • Software-Hardware Mapping • Internal/external connectivity • Efficient Resource Management • Reconfiguration Management Topics Addressed SDR: Computing Management
10. Servicios de Comunicaciones Robustez, Isocronismo, Multiples Servicios (Bandas, Modos), Bridging Aplicaciones Radio Codificación Decodificación Fuente Servicios y Soporte de Red INFOSEC Codificación Decodificación Fuente Modem IF Processing RF Channel Access Formas de onda especificas Infraestrucrtura Real -Time CORBA/IDL Capa Tunel Capa JAVA Conflictos Gestión Recursos Middleware Arquitectura Abierta Control Conjunto Detección de Conflictos Hardware FPGA ADs y DAs ASICs Multiples Multiples OS Nivel de Sistema Operativo Filtro Demod Plataforma Hardware Communication Services Robustness, Isochronisms, Multiples Services, Bridging, Applets/Scripts, Low-Cost Upgrades (Over-the-Air-Downloads) Radio Applications Codificación Decodificación Fuente Services and Network Support INFOSEC Source Coding Modem IF Processing RF Channel Access Specific Waveforms Radio Infrastructure Software Layer, Interface Radio JAVA Layer Conflicts Resource Management Middleware Open Architecture Common Control Conflicts Detection Hardware FPGA ADs and DAs ASICs Multiples DSPs and GPPs Multiples OS Operating System Level Filter Demod Hardware Platform Radio Platform Layered Approach SDR: Computing Management
11. SDR Requirements (Management) ‰Software Framework ‰ Implementation of a Radio Application independently of hardware: Hardware Abstraction Layer (HAL). ‰ Define a Virtual Context not related to any particular hardware architecture. ‰ Hide processor and platform heterogeneity to the radio application. ‰ Run-Time and Development support ‰Capacity to load the required software on each processor. ‰Software scheduling, mapping, etc. ‰Software monitoring. ‰Specific Libraries for each hardware platform. SDR: Computing Management
12. HAL Hardware Operating System Services OS API Application Different Layer Views OS Layer Stack Platform 2. e.g. with API for communications HW HW HW Abstraction Abstraction Abstraction Different Abstraction Depths Application P-HAL Layer Stack P-HAL Abstraction Level Platform 3. e.g. with OS Platform 1. e.g. pure hardware P-HAL Concept SDR: Computing Management
13. Execution Approach ƒ DSP and FPGA offer a different execution paradigm ƒ DSP: time-division ƒ FPGA: area-division Very different P-HAL Implementation T1 T2 T3 T4 T5 P-HAL front-end P-HAL local Dispatch kernel Tasks P1 P-HAL local Dispatch kernel Tasks P2 P-HAL local Dispatch kernel Tasks P3 P-HAL local Dispatch kernel Tasks P4 DSP4 DSP3 DSP2 DSP1 Local bus I/O Interface VME Interface P-HAL front-end P-HAL local Dispatch kernel Tasks P1 P-HAL local Dispatch kernel Tasks P2 P-HAL local Dispatch kernel Tasks P3 P-HAL local Dispatch kernel Tasks P4 DSP4 DSP3 DSP2 DSP1 Local bus I/O Interface VME Interface Sequential Execution DSP FPGA Parallel Execution T1 T2 T3 T4 T5 SDR: Computing Management
14. APPLICATION OBJECTS VHD VHD C C P-HAL Solaris P-HAL Linux P-HAL DSP (P4291) P-HAL FPGA (SHaRe) P-HAL SOFTWARE LOAD LAYER Development Flow ‰ DSP and FPGA have a different development flow. Drawback!! Common Description Language SDR: Computing Management
15. OUTPUT SDR: Computing Management DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Not needed Not needed DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 4 4 4 Not needed Not needed Not needed Not needed DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Not needed Not needed DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 4 4 4 Not needed Not needed Not needed Not needed MF I-Q SR CHIP SYNC
16. OUTPUT SDR: Computing Management P5 P1 P2 P3 P8 P10 P4 P6 P7 P11 AD/DA Converter DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Not needed Not needed DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS 10MOPS Matched Filter 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 DDS Sampling Rate Sampling Rate Frequency Adjust Ray Search Ray Search 2450MOPS 492MOPS 120MOPS 130MOPS 1MOPS Interpolator Decimator 46 MOPS 492MOPS 2450MOPS 160MOPS 4-Finger RAKE MRC MRC Channel Estimation 92MOPS Channel Estimation 92MOPS DCH f < 1KHz fs = 61.44MHz fs = 61.44MHz fs = 15.36MHz fs = 3.84MHz Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Chip Sync. 4 x 4000MOPS Maximum Search Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 Sync1 Sync2 Sync1 Sync1 Sync4 Sync3 fs = 65MHz fs = 65MHz 2nd Inter- leaving 2nd Inter- leaving 1st Insertion of DTX Indication CRC Physical Channel Mapping Physical Channel Segmen- tation 10MOPS Radio Frame Segmen- tation 63MOPS 1st Inter- leaving 116MOPS Rate Match- ing 141MOPS Turbo De- coding 342MOPS TrBk Concat./ CodeBk Segment. 11.7MOPS 0.2MOPS 0.384MBPS 0.384MBPS 1.15MBPS 1.15MBPS (480*16)kbps 105MOPS 2nd Insertion of DTX Indication 2nd Insertion of DTX Indication Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 Matched Filter 4 4 Matched Filter 4 4 Matched Filter 4 4 4 4 Not needed Not needed Not needed Not needed MF I-Q SR CHIP SYNC TC INTER-PROCESSORS SYNCHRONISATION DATA ROUTING Latency MAPPING
17. Modularity: Object-Oriented Programming ‰ An application is made of several objects running independently on one or more processors. ‰ Each object interfaces with other objects through FIFO-like interfaces. ‰ Interfaces carry packets of data. Data represent samples of signals. The meaning of samples is contextual: waveform samples, symbols, bits, characters, etc. ‰ An object only uses P-HAL API to access the external resources (parameters, etc.) or to use the physical interfaces. ‰ A physical interface is defined including information like bits per sample, samples per second, logic format of data, etc. SDR: Computing Management
18. Message-Passing-Oriented Architecture Basic object processing loop: for ever { packet=read(MY_INPUT); result=process_data(packet); write(MY_OUTPUT,result); } Loop is executed once for every data packet that arrives to the object. SDR: Computing Management
19. ‰ When more than one platform with P-HAL compliant mechanisms are put together, a larger virtual platform is created. ‰ This virtual platform offers the same facilities than a bigger platform with its own P-HAL. Virtual Layer P-HAL Platform 2 Platform 3 Platform 4 Platform 1 Hardware Layer Platform Software Layer P-HAL Kernel Sync Bridge Stats P-HAL Kernel SW Map Sync Bridge Stats Physical Interfaces P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats SDR: Computing Management Joining Multiple Platforms (BRIDGE)
20. BRIDGE Routing ‰ The architecture of connections between platforms is not necessarily the “full connectivity” one. ‰ Routing mechanisms for P-HAL packets are necessary within BRIDGE. For instance, packet from object in 3 to object in 1 routed by BRIDGE in 2: Linux Box FORCE 5V microSPARC II PENTEK 4291 Quad-C6701 SHaRe v1.0 Octal-XC4013 A/D/A VME bus IP link 4 1 2 3 5 SDR: Computing Management
21. BRIDGE Routing Establishment From a topology file P-HAL generates the graph of connections. The graph for the previous example would be: 1 3 2 4 5 Network Bus Bus Bus Dedicated Dedicated Routing graphs (or tables) are distributed to all P-HAL platforms. SDR: Computing Management
22. Temporal control (SYNC) ‰ For the large virtual platform, distribution of adequate time references is necessary. Each platform has its own time counter (or RTC) that must be aligned with other time counters. ‰ The references can be obtained only through communications interfaces. That is, precision in synchronism is based on communications reliability. ‰ Synchronism is performed regularly to overcome the differences in the respective local oscillators. ‰ Time adjustment is crucial for the correct behaviour of the application but a relatively slight misalignment is not critical because of the execution time framework. SDR: Computing Management
23. Execution Control (SYNC) ‰ Time is divided into time slots to control the temporal evolution of applications. ‰ PIPELINED execution. ‰ Every application object gets CPU time within every time slot to process data packets. P-HAL schedules the execution of the object. The instant within the slot where the object goes to execution is immaterial. SDR: Computing Management
24. Execution Control (SYNC) SDR: Computing Management P P P P P Object 1 Object 2 Object 3 Object 4 Object 5 Processor 1 Objects Processor 2 Objects Processor 1 Data T O1 to O2 1 2 1 2 P P P 3 5 4 P 5 4 3 5 4 P 5 3 5 4 P 5 4 2 1 P P P-HAL Process Schedule 1 Slot Data Transfer 1 Slot Processor 2 1 Slot Data T O2 to O4 Data Transfer Data Transfer Data Transfer Data Transfer N N+1 N+2 P P P P P Object 1 Object 2 Object 3 Object 4 Object 5 Processor 1 Objects Processor 2 Objects Processor 1 Data T O1 to O2 1 2 1 2 P P P 3 5 4 P 5 4 3 5 4 P 5 3 5 4 P 5 4 2 1 P P P-HAL Process Schedule 1 Slot Data Transfer 1 Slot Processor 2 1 Slot Data T O2 to O4 Data Transfer Data Transfer Data Transfer Data Transfer P P P P P Object 1 Object 2 Object 3 Object 4 Object 5 Processor 1 Objects Processor 2 Objects Processor 1 Data T O1 to O2 1 2 1 2 P P P 3 5 4 P 5 4 3 5 4 P 5 3 5 4 P 5 4 2 1 P P P-HAL Process Schedule 1 Slot Data Transfer 1 Slot Processor 2 1 Slot Data T O2 to O4 Data Transfer Data Transfer Data Transfer Data Transfer N N+1 N+2
25. Synchronism procedure (SYNC) TG1 Time Reading TG3 Time Reading Time Setting TP1 TP2 TG2 TR SLAVE SYNC MASTER SYNC Local Reference Remote Reference Time Reading TGR1 TGR2 TS1 TGR3 ∆TA ∆TE TG1 Time Reading TG3 Time Reading Time Setting TP1 TP2 TG2 TR SLAVE SYNC MASTER SYNC Local Reference Remote Reference Time Reading TGR1 TGR2 TS1 TGR3 ∆TA ∆TE ∆TE SLOT n+1 SLOT n SLOT n+1 SLOT n Platform 2 MASTER SYNC SALVE SYNC Platform 1 ∆TE SLOT n+1 SLOT n SLOT n+1 SLOT n Platform 2 SDR: Computing Management
26. Object execution sequence Initialisation. No real-time required Read Configuration Set-up Communications Set-up Statistics Register to P-HAL INIT Close Resources STOP analyse message if any dispatch task if any return Unregistered P-HAL RUN START EXIT Tx Status Status Hard real-time Exit. No real-time required SDR: Computing Management
27. The API adaptation to FPGA OBJECT P-HAL INTERFACE SWITCH (ROUTING TABLE) DATA LOGICAL INTERFACES: FIFO-LIKE PHYSICAL INTERFACES P-HAL RAM ADAPTATION LOGICAL RAM INTERFACE SBSRAM SDRAM SRAM MEMORY POOL ENABLE/DISABLE/RESET STATUS MONITOR P-HAL CONTROL PORT CONTROL WORD (4 – 8 bits) BIDIRECTIONAL SERIAL PORT FOR REQUESTS (IN/OUT) PHYSICAL INTERFACE TIME REGISTER TIME STAMP ON-BOARD TIME INTERFACE SDR: Computing Management
28. The API adaptation to FPGA BIG FPGA COMON P-HAL OBJECT 1 OBJECT 2 SMALL FPGA SINGLE P-HAL OBJECT 2 SMALL FPGA SINGLE P-HAL OBJECT 1 A single FPGA can be shared by multiple objects if development tools can separate configuration for them. Single-threaded FPGAs can easily exchange the running object but introduce more overhead.. SDR: Computing Management
29. P-HAL Included Mechanisms ‰Real-time seamless exchange of information from one P-HAL compliant platform to another (BRIDGE). ‰Isochronisms of data and processes running on different platforms (SYNC). ‰Platform-wide coordinated process control, scheduling, logging and error control (KERNEL). ‰Start/Stop object execution on a given process (KERNEL). ‰Real-time system monitoring, data and statistics capture and adaptation of processes by means configuration parameters (STATS). SDR: Computing Management
30. P-HAL General View Application Defined as a set of object tasks running concurrently and having FIFO-like interfaces. Objects do not interact each other. Only P-HAL interface is viewed. P-HAL offers the same view to the application independently of number and type of underlying platforms. Platform 2 Platform 3 Platform 4 Platform 1 Hardware Layer Platform Software Layer Virtual Layer P-HAL Kernel Sync Bridge Stats P-HAL Kernel SW Map Sync Bridge Stats Overall P-HAL Task 1 Task 2 Task 3 Task 4 Task 5 Task 6 Real Application Layer Abstract Application Layer Object Task 1 Object Task 2 Object Task 3 Physical Interfaces P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats Object Task 4 Object Task 6 Object Task 5 Platform 2 Platform 3 Platform 4 Platform 1 Hardware Layer Platform Software Layer Virtual Layer P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats P-HAL Kernel SW Map Sync Bridge Stats P-HAL Kernel SW Map Sync Bridge Stats Overall P-HAL Task 1 Task 2 Task 3 Task 4 Task 5 Task 6 Real Application Layer Abstract Application Layer Object Task 1 Object Task 2 Object Task 3 Physical Interfaces P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats P-HAL Kernel Sync Bridge Stats Object Task 4 Object Task 6 Object Task 5 SDR: Computing Management
31. The P-HAL API Control functions: InitPHAL Status ClosePHAL Relinquish Communications functions: CreateFlow WriteFlow ReadFlow GetFlowStatus DeleteFlow Initialisation functions: ReadInitFile GetParameter Event register functions: CreateLog WriteLog, WriteMsg, WriteVar CloseLog Statistics functions: InitStatistics CreateStat SetStatValue GetStatValue DeleteStat Other functions: GetTimeStamp UnrecoveryError STOP RUN INIT SDR: Computing Management
32. ‰Execution and Control Plane separation (virtual) ‰Radio algorithms does not know its environment. ‰Software Blocks use P-HAL API to access to any offered functionality. Introduce overhead! Object 1 Object 2 Object 3 Object 4 Object 5 Monitoring and Control Plane P -HAL component Execution Plane P-HAL component Resource Algorithm Kernel Object 1 Object 2 Object 3 Object 4 Object 5 Monitoring and Control Plane P -HAL component Execution Plane P-HAL component Resource Algorithm Kernel SDR: Computing Management
33. P-HAL Overhead ‰DSP devices (C6701 DSP): Two types of overhead ‰Cycles consumed in accessing P-HAL kernel services (100 cycles) less than 0.1% ‰Cycles required by P-HAL kernel to switch from one object to another (scheduling) (200 cycles) ‰less than 0.2% ‰Scenario: 4 object tasks in one DSP requesting a mean of six services per time slot only 3.2% of DSP cycles for P-HAL ‰FPGA Devices (1 million gates): Overhead 0.5% SDR: Computing Management
34. Temporal Issues: Overhead & Latency 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 10 20 30 40 50 60 70 80 90 100 Overhead (%) Time Slot Length (µs) 5 Objects 10 Objects 15 Objects 20 Objects Latency (ms) 100 90 80 70 60 50 40 30 20 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 0 50 45 40 35 30 25 20 15 10 5 0 20 Objects 15 Objects 10 Objects 5 Objects Example from measurements on Pentek 4291 DSP platform SDR: Computing Management
35. • Middleware hiding processing platforms heterogeneity. • Systematics in developing Radio Modules: Object Oriented Approach • Real-Time Computing Assumptions • Facilitates Dynamic Reconfiguration • Computing Management in SDR environments SDR: Computing Management Summary: