DE RENNES 18 Outils de conception LISATek RESOURCE{ REGISTER unsigned FPC; RAM unsigned prgMem{ SIZE(0x1000); BLOCKSIZE(32,32); } … PIPELINE pipe = {FE;DC}; } LISA 2.0 Model Analyze LISA Processor Designer Generate Build Design goals met ? no yes Co- simulation Software- tools RTL implementation (VHDL,Verilog) Application Simulator C-Compiler Linker Assembler Architecture Debugging & Profiling